1. Field of the Invention
This invention relates generally to high-speed digital data transmission, and more particularly to a coding and framing method for digital data transmission.
2. Description of Related Art
Digital data is often transmitted from one device to another device as a digital sequence. In its simplest form, a digital sequence is a transmission pattern formed using a time sequence made up of “pulses” of two signal types, representing two binary symbols (a zero and a one). In an electrical transmission system, the sender may send one voltage to represent zero, and another voltage to represent one, each bit represented by the appropriate voltage during its corresponding bit time. Such a system can also be differential, i.e., a pair of electrical conductors is used, with one of the pair sending the opposite signal as the other of the pair, both conductors active during each bit time. By detecting and differentiating between the two signal types sent by the sender and recovering the timing of a transmitted sequence, a receiver can reconstruct the original digital data sequence.
Since from a flexibility standpoint the digital data input sequence is preferably unconstrained as to its content, some allowable input sequences may cause problems at the receiver if sent without modification. For instance, if the receiver is to recover timing information from the transmitted data, a certain number of data transitions (one to zero or zero to one) per unit time are required. A long string of zeros or ones in the input data may allow the receiver timing to drift, causing bit errors. Also, if an electrically transmitted signal is not dc-balanced (i.e., an equal numbers of zeros and ones are transmitted over time), the transmitter and receiver cannot be dc-coupled, or else the signal levels representing a zero and a one will drift. Further, were the channel susceptible to any of these conditions, a malicious sender could intentionally attack the transmission system by sending a data sequence with a pattern designed to confuse the receiver.
To solve these and other problems (such as how to detect and/or correct transmission errors at the receiver), many digital data transmission systems employ transmission coding. The transmission code adds some overhead bits and/or characters to the input sequence, and manipulates the input sequence to avoid one or more of the aforementioned problems.
One transmission code in wide use today is the 8b/10b transmission code as disclosed by Franaszek and Widmer in U.S. Pat. No. 4,486,739, “Byte Oriented DC Balanced (0,4) 8b/10b Partitioned Block Transmission Code.” The 8b/10b transmission code (“8b/10b code”) accepts an input sequence of eight-bit blocks, and transforms each eight-bit block into a ten-bit codeword. Each ten-bit codeword contains either six ones and four zeros, five ones and five zeros, or four ones and six zeros, with a maximum design spacing between adjacent zero-to-one and one-to-zero transitions in each codeword to allow the receiver to maintain timing. Each input value that can be coded with a codeword having six ones and four zeros can also be coded with a codeword having four ones and six zeros. One of those two codewords is selected for transmission by a rule that nulls any running zero-to-one disparity in the transmitted sequence. By following the same rules as the transmitter, the receiver decodes the codewords to recover the eight-bit blocks of the input sequence.
The 8b/10b code also provides some ten-bit codewords that represent channel control characters. Some of these characters contain a “comma” property, i.e., they contain a bit pattern that can only occur within such a codeword and not across any two other consecutive characters. These comma characters are useful for instantaneous byte synchronization at the receiver. One pair of such control words are commonly referred to as “K” and “R”, representing even and odd idle characters. Other typical control words include an align character “A”, which can be used to align data transmitted on multiple parallel bit lanes.
One drawback associated with 8b/10b coding is its high coding overhead. For every eight-bit input value, ten bits are transmitted across the channel. Factoring in the added control words, more than 20% of the channel's physical bit capacity is consumed by the 8b/10b code overhead. FIG. 1 depicts a typical relationship between the input 10 to an 8b/10b coder 12, and the coder output 14 actually sent on the channel. Not only must 10 bits be allocated in the transmit channel for each coded version Cn of an eight-bit data input value Dn, but control characters K also occupy significant numbers of bit times on the transmit channel.
For 10 Gb/s (gigabits/second) Ethernet, a different coding scheme is used to avoid the high coding overhead of the 8b/10b code. This coding scheme, commonly referred to as 64b/66b coding, is described by Walker et al. in European Patent Application EP 1133124A2, entitled “Coding for Packetized Serial Data.” 64b/66b coding achieves a more efficient use of the channel than 8b/10b coding—for each 64-bit input block, only 66 bits are transmitted. The 66 bits comprises a two-bit block type code and 64 bits of scrambled data and control words.
Referring to FIG. 2, an input sequence 20 comprises 64-bit blocks B1 and B2. Block B1 contains only input data, more specifically eight data bytes D1-D8. A type pattern generator 26 detects that all bytes in block B1 are data, and therefore generates a data “type” to a frame composer 22 and a two-bit block type code T1 with a value “01” to a transmitter 28. A data type frame requires no transformation by frame composer 22, and therefore frame composer 22 sends the 64-bit data to a scrambler 24 as a formatted frame F1. Scrambler 24 uses an x58+x39+1 scrambler on formatted frame F1 to produce a 64-bit scrambled frame S1, which is also supplied to transmitter 28. Transmitter 28 prepends the two-bit block type code to the 64-bit scrambler output and transmits 66 bits on a channel 29. The receiver (not shown) at the opposite end of channel 29 interprets the two-bit block type code, and simply descrambles the following 64 bits to produce an input 64 bits descrambled frame. The two-bit block type code signifies that the descrambled frame comprises only data bytes.
When a 64-bit block contains one or more control words, such as block B2, coding and decoding complexity is increased. The block could contain all control words, or could contain mixed data and control words, as block B2 illustrates. A finite number (10) of different mixed data/control symbol arrangements are allowed, one of which (a single data symbol D9 followed by a packet termination symbol T and a string of other control symbols) is illustrated. In such a circumstance, type pattern generator 26 produces an eight-bit frame type code FT to frame composer 22 and a two-bit block type code T2 with a value “10”—opposite the code used for information-data only. The frame type code FT describes the ordering of information and control words in the 64-bit block, and also describes at least one control word. In this particular example, the frame type code FT describes the mixed data/control sequence consisting of one data word, followed by a termination symbol, followed by other control words. Frame type code FT is coded as the first eight bits of the 64-bit formatted frame F2 sent by frame composer 22 to scrambler 24. The second eight bits of F2 contain the single data word D9. The termination symbol is understood from the value of FT. The remaining six control words are coded as seven-bit control words and placed in specific locations in the remaining 48 bits of frame F2. Scrambler 24 scrambles block B2 to produced scrambled frame S2. Transmitter 28 prepends block type code T2 (“10”) to scrambled block S2 and place the 66-bit frame on channel 29. The receiver interprets the “10” two-bit block type code as indicating that the block will require additional decoding after descrambling. The type code from the descrambled data is interpreted, allowing the receiver to restore the original 64 bits of control and information words from the descrambled data.
One difficulty with the 64b/66b code is that because 64 of every 66 bits are scrambled—and the 64 scrambled bits include the control code characters—the 64b/66b code has no “comma” control character that allows easy block synchronization of transmitter and receiver. As a result, it may take long periods of time involving hunting and guessing to synchronize or resynchronize the channel should the channel become desynchronized.